The present invention is related to memory devices. More particularly, the present invention is related to SDRAM (synchronous dynamic random access memory).
One common type of memory is SDRAM. The structure and operation of SDRAM is well known. In overview, an SDRAM has a number of addressable memory locations that depends on the total size of the SDRAM and the size of each memory location. Each addressable memory location has a corresponding memory address. For example, an 8 MB (megabyte) SDRAM where each location is 32 bits has 2,097,152 addressable locations, while an 8 MB SDRAM where each location is 8 bits has four times as many addressable locations. One example of a conventional SDRAM is 2M×32 SDRAM MT48LC2M32B2 by Micron Technology, Inc.
FIG. 1A is a representation of 2,097,152 memory locations as a one-dimensional array 105. Memory cells in a typical SDRAM are physically arranged in a two-dimensional grid and so individual cells or groups of cells (i.e., memory locations) can be identified using a combination of a row number and a column number. The memory locations within the same row are often collectively referred to as a “page.” FIG. 1B is a representation of 2,097,152 memory locations as a two-dimensional array or grid 150 having X columns 155 and Y rows 160. In FIG. 1B, X is 256 and Y is 8192. Accordingly, grid 150 has 256 columns 155, from 0 to X−1, and 8192 rows or pages 160, from 0 to Y−1. The location in row y at column x has address (y*X+x). For example, location 165 (the first location in the last page) has address (X*(Y−1)) and location 170 (the last location in the last page) has address (X*Y−1). The sizes of the boxes representing locations in FIG. 1B are representative and not to scale, so different size boxes are not different size memory locations (e.g., locations 165 and 170).
An address for a memory location can be viewed as a combination of a row address and a column address. FIG. 1C is a representation of an address 175 for one memory location out of 2,097,152. Address 175 has 21 bits, with A0 as the lowest order bit. The lower 8 bits, A0 to A7, are a column address 180, ranging from 0 to 255. The upper 13 bits, A8 to A20, are a row or page address 185, ranging from 0 to 8191.
Due to the nature of the construction of SDRAM, an entire page of memory cells is active at a time. Accessing cells within the same active page can be accomplished relatively quickly using a series of column addresses without changing the page address and activating a new page. To change pages, a new page address is used and an additional delay is incurred from both the extra address cycle and a delay in the memory changing which page is active. This delay is referred to as a “page miss” and can result in a loss in speed.